Professional Summary

Yongwon Lee is a member of the research faculty in the George W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology, where he serves as a Senior Research Engineer in the 3D Systems Packaging Research Center. His research addresses advanced semiconductor packaging for artificial intelligence (AI) and high-performance computing (HPC), with a focus on glass-core substrates, large-area package assembly, and thermomechanical reliability.

Lee brings 23 years of industrial experience from ASE and Samsung Electronics, where he served as a Principal Engineer and Director and led the development and commercialization of advanced packaging technologies for high-volume mobile products. His contributions to industry have been recognized with the IR52 Jang Young Shil Award, and he holds more than 80 patents worldwide.

He joined Georgia Tech in 2022, where his work connects manufacturing practice with fundamental reliability research to enable scalable heterogeneous integration. Lee received his Ph.D. from The University of Osaka and is a Senior Member of the IEEE.

Research Interests

  • Glass-core substrates and large-area package assembly for AI/HPC
  • Thermomechanical and board-level reliability of advanced packages
  • 2.5D/3D advanced packaging and heterogeneous integration

Distinctions and Awards

Technology and Industry Awards

  • IR52 Jang Young Shil Award, Ministry of Education, Science and Technology, Korea, 2012
  • Samsung Award of Honor – Technology Award, Samsung Electronics, 2012
  • Samsung Outstanding Achievement Award, Samsung Electronics (6 times: 2010, 2011, 2012, 2013, 2016, 2019)

Best Paper Awards

  • Samsung Best Paper Award (Bronze), Samsung Electronics, 2017
  • Highly Commended Paper Award, Soldering & Surface Mount Technology, 2012
  • NXP Semiconductors Best Paper Award, IEEE ICEPT-HDP, Shanghai, China, 2008

Recent Publications

  • Y. Lee, "Influence of surface roughness on the strength and microstructure of vacuum brazed SUS304 using BNi-2 filler metal," Mater. Trans., vol. 66, no. 9, pp. 1174–1185, 2025, doi: 10.2320/matertrans.MT-M2025037.
  • S.-J. Paik, K.-S. Moon, Y. Lee, and S. J. Hong, "Process metrology and validation for 3D advanced packaging: A comprehensive review," J. Korean Soc. Manuf. Process Eng., vol. 25, no. 1, pp. 124–136, Jan. 2026, doi: 10.14775/ksmpe.2026.25.1.124.
  • Y. Lee, K. Godbole, H. Park, K.-S. Moon, M. Bakir, and S. K. Sitaraman, "Board-level reliability of 100 × 100 mm large glass packages: Warpage and thermomechanical reliability for AI/HPC applications," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 16, no. 2, pp. 330–342, Feb. 2026, doi: 10.1109/TCPMT.2025.3614186.
  • Y. Lee, "Automotive reliability benchmarks for high-lead Pb–Sn–Ag die attach in PQFN power packages: Implications for Pb-free transition," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 16, no. 6, pp. 1456–1465, Jun. 2026, doi: 10.1109/TCPMT.2026.3666744.