• Ph.D., The Ohio State University, 1989
  • M.A.Sc., University of Ottawa, Canada, 1985
  • B.E., University of Madras, India, 1982

Research Areas and Descriptors


Dr. Sitaraman began at Tech in 1995 as an Assistant Professor. Prior, he was at IBM Corporation.


Array of microscale (typical dimensions: 8 μm thick and 11 μm wide, and 75-90 μm tall) and nanoscale (typical dimensions:  50-100 nm wide, 30 nm thick, and 1000 nm long), freestanding structures for microelectronic packaging, probing, and disease diagnostic and bio-sensing applications.

Dr. Suresh Sitaraman and George Lo (B.S. University of Washington, M.S. Georgia Tech) are discussing microvia processing and reliability for electronics packaging applications.

Dr. Sitaraman's research is in the areas of micro- and nano-scale structure fabrication, characterization, physics-based modeling and reliable design. His micro- and nano-scale research focuses on a wide range of application areas such as aerospace and defense, automotive, computers and telecommunications, portable electronics, and medical. In particular, his research is developing micro-scale and nano-scale structures that can be used as compliant packaging interconnects. Such interconnects can also be used as bio-assays for cancer diagnosis and to determine the efficacy of cancer treatment. His research is also developing innovative stressed super layer techniques to determine the interfacial strength of thin structures ranging from 5 nm to 1-2 um. Dr. Sitaraman's research also aims to understand the long-term reliability of lead-based and lead-free solder interconnects through thermo-mechanical modeling, material microstructure evolution, reliability experiments, and laser moire interferometry. In parallel, Dr. Sitaraman's research focuses on the next-generation integrated substrates that have high-density interconnects and microvias, embedded passives, and optoelectronic waveguides. In particular, Dr. Sitarman's group has done work in material length scale effects for microvia reliability, cure kinetics and interlayer dielectric cracking and delamination, reliability modeling and experiments for embedded passives and optical waveguides. Visit for more information about his research.


  • Thomas French Achievement Award, Department of Mechanical and Aerospace Engineering, The Ohio State University, 2012
  • American Society of Mechanical Engineers
    • Applied Mechanics Award, Electronic and Photonic Packaging Division, 2012
    • Fellow, 2004
    • International Congress Symposium Chair, 1997
  • Georgia Institute of Technology
    • Sigma Xi (Georgia Tech Chapter) Sustained Research Award, 2008
    • Outstanding Faculty Leadership Award for the Development of Graduate Research Assistants, 2006
    • Packaging Research Center Outstanding Faculty Educator Award, 1998
    • Packaging Research Center Technology Program Award, 1998
  • Institute of Microelectronics and Packaging Society
    • International Symposium on Advanced Packaging Materials Best Paper of the Session, 2000 and 1999
  • Institute of Electrical and Electronics Engineers
    • Transactions of Advanced Packaging Commendable Paper Award, 2004
    • Transactions on Components and Packaging Technologies  Best Paper of the Year, 2001 and 2000
    • Transactions on Compoents, Packaging, and Manufacturing Technology,  Associate Editor
  • Metro Atlanta Engineer of the Year in Education, 1999
  • National Science Foundation Faculty Early Career Development Award, 1997-2002
  • National Institute of Standards and Technology Advanced Technology Program Award, 1998


  • Kacker, K., Sokol, T., and Sitaraman, S. K., “Variable Interconnect Geometry for Electronic Packages and Fabrication Methods,” U. S. Patent No. 8,766,449 B2, July 1, 2014.
  • Kacker, K. and Sitaraman, S. K., “Compliant Off-Chip Interconnects for Use in Electronic Packages and Fabrication Methods,” U. S. Patent No. 8,382,489 B2, Feb. 26, 2013.
  • Kacker, K. and Sitaraman, S. K., “Compliant Off-Chip Interconnects for use in Electronic Packages,” U. S. Patent No. 8,206,160 B2, June 26, 2012.
  • Sitaraman, S. K., Ma, L., and Zhu, Q., “Multi-Axis Compliance Spring,” U.S. Patent No. 7,011,530, March 14, 2006.
  • Zhu, Q., Ma, L., and Sitaraman, S. K., “Complaint Off-Chip interconnects,” U.S. Patent No. 6,784,378, August 31, 2004.

Representative Publications

  • Okereke, R. and Sitaraman, S. K., “Mixed Array of Compliant Interconnects to Balance Mechanical and Electrical Characteristics,” ASME Transactions – Journal of Electronic Packaging, Sep. 2015, Vol. 137, pp. 0310061- 0310069.
  • Raghavan, S., Schmadlak, I., Leal, G., and Sitaraman, S., “Study of Chip-Package Interaction Parameters on Interlayer Dielectric Crack Propagation,” IEEE Transactions on Device and Materials Reliability, Vol. 14, No. 1, March 2014, pp. 57-65.
  • Ginga, N. J., Chen, W., and Sitaraman, S. K., “Waviness reduces effective modulus of carbon nanotube forests by several orders of magnitude,” Carbon, Volume 66, January 2014, pp. 57–66.
  • Liu, X., Thadesar, P. A., Taylor, C. L., Kunz, M., Tamura, N., Bakir, M. S., and Sitaraman, S. K.,  "Dimension and Liner Dependent Thermomechanical Strain Characterization of Through-Silicon Vias using Synchrotron X-ray Diffraction," Journal of Applied Physics, Vol. 114, p. 064908, 2013.
  • Ostrowicki, G. T., Fritz, N. T., Okereke, R. I., Kohl, P. A., and Sitaraman, S. K., “Domed and Released Thin Film Construct – An Approach for Material Characterization and Compliant Interconnects,” IEEE Transactions on Device and Materials Reliability,” Vol. 12, No. 1, March 2012, pp. 15-23.
  • Tunga, K. and Sitaraman, S. K., "Fatigue Life Prediction of Lead-free Solders using Laser Moiré Interferometry," Microelectronics Reliability, Vol. 50, Issue 12, Dec. 2010, pp. 2026-2036.
  • K. Kacker, et al. 2007. A Heterogeneous Array of Off-Chip Interconnects for Optimum Mechanical and Electrical Performance. Transactions of the ASME – Journal of Electronic Packaging 129, 460-468.
  • S. Hegde and S. K. Sitaraman. 2007. Stress-Induced Birefringence in Siloxane Polymer Waveguides.Applied Physics Letters 91(8), August.
  • K. Tunga and S. K. Sitaraman. 2007. An Expedient Experimental Technique for the Determination of Thermal Cycling Fatigue Life for BGA Package Solder Balls.
    Transactions of the ASME – Journal of Electronic Packaging 129, 427-433.
  • A. Perkins and S. K. Sitaraman. 2007. Universal Fatigue Life Prediction Equation for Ceramic Ball Grid Array (CBGA) Packages. Microelectronics Reliability 47/9-11, 1353-1367.
  • J. Zheng and S. K. Sitaraman. 2007. Fixtureless Superlayer-driven Delamination Test for Nanoscale Thin Film Interfaces. Thin Solid Films 515(11), 4709-4716.