- Ph.D., The Ohio State University, 1989
- M.A.Sc., University of Ottawa, Canada, 1985
- B.E., University of Madras, India, 1982
Research Areas and Descriptors
- Computer-Aided Engineering and Design, Manufacturing, Micro & Nano Engineering, and Mechanics of Materials
- Fabrication, Testing, and Characterization of Micro- and Nano-Scale Structures, Physics-based Predictive Modeling and Reliable Design, Fatigue and Fracture, Rigid and Flexible Microsystems, Emerging Technologies
Dr. Sitaraman began at Tech in 1995 as an Assistant Professor. Prior, he was at IBM Corporation.
Dr. Sitaraman’s research focuses on fabrication, testing, and characterization of micro- and nano-scale structures, physics-based predictive modeling, reliable design, and development of innovative technologies as applied to rigid and flexible microsystems. For example, Dr.Sitaraman’s research is developing fixtureless magnetic actuation test technique to determine interfacial fracture energy for thin-film structures. In this test, an external electromagnet is used to debond the interface of interest under monotonic and fatigue loading conditions. As no external fixturing is required to apply the load, it is easy to place the sample in a thermal/humidity chamber, debond the interface using an external electromagnet, and thus determine the interfacial fracture energy at different temperature/humidity conditions.
This magnetic actuation technique and other traditional interfacial fracture techniques such as double-cantilever beam test, four-point bend test, and brazil nut test, offer enormous insight into adhesion of dissimilar materials. Such dissimilar materials are commonly used, for example, in rigid electronic systems, flexible electronic systems, photovoltaic systems, implantable medical devices, and others. Fracture mechanics models and cohesive zone models are being developed and used to study various interfacial delamination failures.
Dr. Sitaraman’s research is also developing compliant micro-scale structures that can be used as electrical interconnects as well as thermal interface structures. Various compliant structures having a single or multiple electrical paths have been fabricated, characterized, modeled, and tested to interconnect a chip to a substrate or a substrate to a board. The compliance of the structures can mechanically isolate the chip from the substrate, and thus, reduce the stresses induced in the chip under thermal or mechanical loading compared to the stresses introduced in flip-chip solder bump interconnects with epoxy-based underfill materials.
In addition to electrical interconnects, Dr. Sitaraman’s research group has explored electroplated copper nanowires as well as carbon nanotubes for thermal management and heat removal in microelectronic systems. http://www.me.gatech.edu/featured_sitaramanwaviness
With the increasing focus on flexible electronic systems, Dr. Sitaraman’s group is exploring various printed materials, chip assemblies, mechanical test techniques, and physics-based models to study materials, devices, assemblies, and systems used in flexible hybrid electronic systems. In addition to the challenges commonly seen in rigid electronics, flexible electronics requires additional fabrication, testing, characterization, and modeling approaches to meet the growing demands and emerging applications.
With the continued push toward miniaturization, Dr. Sitaraman’s group is also studying 3D microsystems where chips are stacked on top of one another and are interconnected using through-silicon vias (TSVs) where typically copper is electroplated in silicon trenches. Cracking of silicon dioxide, debonding of copper, copper pumping, copper microstructure changes under thermal excursion, and stacking and assembly of chips are some of the challenges associated with such 3D microsystems. Through computational models, synchrotron x-ray diffraction measurements, and comprehensive experiments, Dr. Sitaraman’s group is studying the reliability issues of through-silicon vias. In addition, Dr. Sitaraman’s group is exploring the use of glass substrates with through-glass vias for microsystem applications.
For details on the Computer-Aided Simulation of Packaging Reliability Lab, please visit www.caspar.gatech.edu
For details on Flexible Hybrid Electronics, please visit www.flex.gatech.edu
- Thomas French Achievement Award, Department of Mechanical and Aerospace Engineering, The Ohio State University, 2012
- American Society of Mechanical Engineers
- Applied Mechanics Award, Electronic and Photonic Packaging Division, 2012
- Fellow, 2004
- International Congress Symposium Chair, 1997
- Georgia Institute of Technology
- Sigma Xi (Georgia Tech Chapter) Sustained Research Award, 2008
- Outstanding Faculty Leadership Award for the Development of Graduate Research Assistants, 2006
- Packaging Research Center Outstanding Faculty Educator Award, 1998
- Packaging Research Center Technology Program Award, 1998
- Institute of Microelectronics and Packaging Society
- International Symposium on Advanced Packaging Materials Best Paper of the Session, 2000 and 1999
- Institute of Electrical and Electronics Engineers
- Transactions of Advanced Packaging Commendable Paper Award, 2004
- Transactions on Components and Packaging Technologies Best Paper of the Year, 2001 and 2000
- Transactions on Compoents, Packaging, and Manufacturing Technology, Associate Editor
- Metro Atlanta Engineer of the Year in Education, 1999
- National Science Foundation Faculty Early Career Development Award, 1997-2002
- National Institute of Standards and Technology Advanced Technology Program Award, 1998
- Kacker, K., Sokol, T., and Sitaraman, S. K., “Variable Interconnect Geometry for Electronic Packages and Fabrication Methods,” U. S. Patent No. 8,766,449 B2, July 1, 2014.
- Kacker, K. and Sitaraman, S. K., “Compliant Off-Chip Interconnects for Use in Electronic Packages and Fabrication Methods,” U. S. Patent No. 8,382,489 B2, Feb. 26, 2013.
- Kacker, K. and Sitaraman, S. K., “Compliant Off-Chip Interconnects for use in Electronic Packages,” U. S. Patent No. 8,206,160 B2, June 26, 2012.
- Sitaraman, S. K., Ma, L., and Zhu, Q., “Multi-Axis Compliance Spring,” U.S. Patent No. 7,011,530, March 14, 2006.
- Zhu, Q., Ma, L., and Sitaraman, S. K., “Complaint Off-Chip interconnects,” U.S. Patent No. 6,784,378, August 31, 2004.
- Raghavan, S., Schmadlak, I., Leal, G., and Sitaraman, S. K., “Mixed-Mode Cohesive Zone Parameters for Sub-Micron Scale Stacked Layers to Predict Microelectronic Device Reliability,” Engineering Fracture Mechanics, Vol. 153, March 2016, pp. 259-277.
- McCann, S., Sato, Y., Sundaram, V., Tummala, R. R., and Sitaraman, S. K., “Prevention of Cracking from RDL Stress and Dicing Defects in Glass Substrates,” IEEE Transactions on Device and Materials Reliability, 2015, DOI: 10.1109/TDMR.2015.2507978.
- Okereke, R. and Sitaraman, S. K., “Mixed Array of Compliant Interconnects to Balance Mechanical and Electrical Characteristics,” ASME Transactions – Journal of Electronic Packaging, Sep. 2015, Vol. 137, pp. 0310061- 0310069.
- Ginga, N. J., Chen, W., and Sitaraman, S. K., “Waviness reduces effective modulus of carbon nanotube forests by several orders of magnitude,” Carbon, Volume 66, January 2014, pp. 57–66.
- Liu, X., Thadesar, P. A., Taylor, C. L., Kunz, M., Tamura, N., Bakir, M. S., and Sitaraman, S. K., "Thermomechanical Strain Measurement by Synchrotron X-ray Diffraction and Data Interpretation for Through-Silicon Vias," Applied Physics Letters, Vol.103, p.022107, 2013.
- Tian, Y., Liu, X., Chow, J. Wu, Y-P, and Sitaraman, S. K., “Comparison of Sn-Ag-Cu Solder Alloy Intermetallic Compound Growth under Different Thermal Excursions for Fine-Pitch Flip-Chip Assemblies,” Journal of Electronic Materials, Vol. 42, No. 8, 2013, pp. 2724-2731.
- Ginga, N. J. and Sitaraman, S. K., “The experimental measurement of effective compressive modulus of carbon nanotube forests and the nature of deformation,” Carbon, Volume 53, March 2013, pp. 237–244.
- Liu, X, Chen, Q., Sundaram, V., Tummala, R. R., and Sitaraman, S. K., “Failure Analysis of Through-Silicon Vias in Free-standing Wafer under Thermal-Shock Test,” Microelectronics Reliability, Volume 53, Issue 1, January 2013, pp. 70–78.
- Ostrowicki, G. T. and Sitaraman, S. K., “Magnetically actuated peel test for thin films,” Thin Solid Films, 520 (2012), pp. 3987–3993.
- Tunga, K. and Sitaraman, S. K., "Fatigue Life Prediction of Lead-free Solders using Laser Moiré Interferometry," Microelectronics Reliability, Vol. 50, Issue 12, Dec. 2010, pp. 2026-2036.
- Hegde, S. and Sitaraman, S. K., “Stress-Induced Birefringence in Siloxane Polymer Waveguides,” Applied Physics Letters, Vol. 91, No. 8, Aug. 2007.
- Zheng, J. and Sitaraman, S. K., “Fixtureless Superlayer-driven Delamination Test for Nanoscale Thin Film Interfaces,” Thin Solid Films, Volume 515, Issue 11, April 2007, pp. 4709-4716.