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GOKCE GURUN Ph.D. Student, Research Assistant Work Phone: (404) 894-2010
Education:
Research Projects:
To meet the demands of medical ultrasound imaging using high density arrays with CMUT technology, specialized integrated circuits should be custom designed. Parasitic capacitances associated with the interconnect lines are an order of magnitude larger than the sensor capacitances degrading the receive sensitivity. Integrating the custom designed ASICs with the CMUT array minimizes the effects of those parasitic connections increasing the SNR. Hence CMOS-ASICs should be custom designed to interface with CMUT arrays. For the first iteration of CMUT-ASIC integration a custom IC in 0.5µm CMOS process is designed. Each 1.5mm2 ASIC contains eight 20kohm gain trans-impedance amplifiers (TIAs) featuring 50MHz bandwidth with 5pF input capacitance, an 8x1 MUX and a buffer amplifier. Four of these ASICs are placed around the transducer array and the electrical connections between array elements and IC chips are provided by wire bonding. A picture of electronic chips and transducer array on the chip carrier is shown in Fig. 1.
Fig.1 Picture of the IC chip (left) and integrated system (right).
Such integration using wirebonding required more than 150 wirebonds for connections which is quite prone to errors. To remove the need for wirebonding and to reduce parasitic capacitances further, a viable approach relies on building CMUTs directly on CMOS electronics (CMUT-on-CMOS). To implement such a system, a custom 8” CMOS wafer is designed in 0.35μm two-polysilicon four-metal CMOS process to monolithically integrate with CMUT arrays. The 8” CMOS wafer contains many reticles of size 2cm × 2cm and each reticle contains many smaller ASICs that are optimized to interface with various transducer arrays (Fig. 2).
Fig.2. Picture of the 8” CMOS Wafer (left), layout and picture of the reticle (right)
A micrograph of an ASIC that is optimized to monolithically interface with a transducer array with 32 receive and 24 transmit elements is shown in Fig. 3. The chip has a die-size of 2 mm × 2 mm. The chip includes 4 sets of pulser arrays, each containing 6 high voltage pulsers. There are 4 sets of receiver arrays. Each receiver array includes 8 transimpedance amplifiers, one 8×1 multiplexer and a buffer to drive cable and pad capacitances. Digital control block is designed to synchronize transmit and receive element operations and includes an 8 bit counter that generates control bits for pulser and receiver arrays. Designed variable gain low noise transimpedance amplifier is measured to have a 770kohms gain, 20MHz bandwidth and 0.16pA/√Hz input referred noise in 0.35μm CMOS.
Fig.3. Micrograph of the ASIC designed for CMUT-on-CMOS
Traditionally high voltage pulses are provided off-chip for ultrasound systems. However, as the monolithic integration of CMUT arrays and the electronics is more desirable, a high voltage pulser is designed utilizing an “Extended Drain NMOS” which is compatible with the fabrication of low voltage devices because it doesn’t require any additional fabrication steps. Layout of designed EDNMOS can be seen in Fig. 4. High voltage Extended Drain NMOS device is designed and fabricated in 0.35μm CMOS process. A breakdown voltage of 35 V is achieved where the breakdown voltage of regular devices in the used technology is less than 10 volts. With a 200fF load, a high voltage pulser which utilizes the designed extended drain NMOS can generate a 35V pulse with a pulse bandwidth of 80MHz.
Fig. 4. Extended Drain NMOS structure
An improved voltage in voltage out low pass Gm-C filter is introduced as an analog delay cell for high frequency dynamic beamformers. This circuit can generate three times more delay with a given bandwidth when compared to conventional low pass filters. Delay of circuit is tunable and the gain of the cell is inherently very close to unity with its current mirror based design. The proposed delay cell operates single ended and therefore is more suitable for CMUT operation which generates single ended output. The CMOS ASIC in Fig. 5 is designed using 0.5μm CMOS process and demonstrates the functionality of the proposed delay element. It includes the delay elements along with 8 transimpedance amplifiers and voltage-to-current converters. Designed delay element demonstrates a tunable 5nsec delay that is constant up to 50MHz. Recently, a 130nm CMOS ASIC featuring an updated version of the delay element is designed and is in fabrication.
Fig. 5. The layout of the ASIC in 0.5μm CMOS process including TIAs and analog delay elements
The ASIC in Fig. 6 is designed using 0.5μm CMOS process and features digital delay circuitry to delay the transmit pulse signals for 8 receive elements. For each receive element there is a delay circuitry that contains a 3-bit counter, a 6-bit shift register where the coarse delay value is loaded, a 3-bit comparator and a fine delay line which can provide 0.5nsec step fine delays. Coarse delay is determined by the value in the shift register which is compared with the counter output. Minimum counter period is 2nsec which determines the coarse delay steps. Final output pulse width is controllable with a pulse extender for different operation frequencies.
Fig. 6. The layout of the ASIC chip and delay circuitry
Designed and tested a reconfigurable sensor interface block in a Field-Programmable Analog Array chip in 0.35μm CMOS process. The chip area is 3mm × 3mm. The layout and the die micrograph are shown in Fig. 7. Designed chip is a powerful tool for fast prototyping sensory microsystems where innovative design ideas can be quickly realized and tested in hardware. This large-scale floating-gate based IC contains 8 universal sensor interface blocks, each of which can be interfaced with different types of sensors. The reconfigurability of the chip is achieved by the Switch Matrix (SM) that connects component terminals to form different circuit topologies.
Fig. 7. The layout and the micrograph of the IC
Conference Papers/Presentations:
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