Charge-Coupled Device Image Sensors

Photo 1. A Kodak technician examines silicon wafers containing image sensors during the manufacturing process. Two Kodak KAI-0371M high-resolution CCD image sensors (right) provided the eyes for the Sojourner rover as it navigated the surface of the planet Mars. A Kodak KAI-0371CM provided full-color images of the ground and soil samples collected by the Sojourner. See sidebar: The Vision of the Sojourner

Like many technologies, the charge-coupled device (CCD) began as one kind of creature and wound up as something completely different. Invented in the late 1960s by researchers at Bell Labs, it was initially conceived of as a new type of computer memory circuit. It soon became apparent that the CCD had many other potential applications, including signal processing and imaging, the latter because of silicon's light sensitivity, which responds to wavelengths <1.1 mm (the visible spectrum falls between 0.4 mm and 0.7 mm). The CCD's early promise as a memory element has since disappeared, but its superb ability to detect light has turned it into the industry-standard image sensor technology.

Like ICs, CCDs begin on thin wafers of silicon processed with a series of steps that define the various functions within the circuit (see Photo 1). On each wafer lies several identical devices, or die, each capable of yielding a functional device. Selected die are then cut from the wafer and packaged in a carrier for use in a system.

Point Scanning. Using a single-cell detector, or pixel (picture element), an image can be scanned by sequentially detecting scene information at discrete X,Y coordinates. This approach delivers high resolution, uniformity of measurement from one site to another, and lower cost and simplicity of the detector. However, point scanning also has disadvantages, which include registration errors from the X,Y movement of scene or detector, lower frame scanning rates (because the repeated number of exposures increases the scanning time), and system complexity (because of the X,Y movement).

Line Scanning. An array of single-cell detectors can be placed along a single axis in such a way that scanning takes place in only one direction. In this case, a line of information from the scene is captured and readout of the device before stepping to the next line index. The physical length of a linear CCD scanner is limited only by the size of the silicon wafer used to make the device. Although this limitation is sometimes overcome by mounting several linear CCDs end to end to increase the overall length, system cost and complexity increases.

The scan time of line scanning is much better than that of point scanning. Other benefits include high resolution and less sophisticated scanning mechanics. However, resolution is limited by the pixel spacing and size in one direction. Measurement accuracy at each pixel has finite nonuniformities that occasionally must be factored out by the system. Scan times, of the order of several seconds or minutes, are still unsuitable for many applications, and the costs of linear CCDs are higher than single-cell detectors.

Area Scanning. You can create a 2-D array of detectors that can capture the entire image with one exposure, eliminating the need for movement by detector or scene. Area scanners can produce the highest frame rates with the greatest registration accuracy between pixels. System complexities are also kept to a minimum. However, resolution is limited in two directions. Other disadvantages include cost and lower signal-to-noise performance because the cost of 2-D array detectors is higher than linear arrays.

Figure 1. In a full-frame CCD, the exposure is controlled by a mechanical shutter or strobe. The resultant charges are shifted one row at a time to the serial register. After a row is read out by the serial register, the next row is shifted to the register for readout. The process is repeated until all rows are transferred, at which point the array is ready for the next exposure.

Full-Frame (FF) Devices. FF CCDs have the simplest architecture and are the easiest to make and operate. They consist of a parallel CCD shift register, a serial CCD shift register, and an signal-sensing output amplifier (see Figure 1).

Images are optically projected onto the parallel array, which acts as the image plane. The device takes the scene information and partitions the image into discrete elements, which are defined by the number of pixels "quantizing" the scene. The resulting rows of scene information are then shifted in a parallel fashion to the serial register, which shifts the row of information to the output as a serial stream of data. The process repeats until all rows are transferred off chip. The image is then reconstructed as dictated by the system.

Because the parallel register is used for both scene detection and readout, a mechanical shutter or synchronized strobe illumination must be used to preserve scene integrity. The simplicity of the FF design yields CCD imagers with the highest resolution and highest density.

Figure 2. In a frame-transfer CCD, the entire array is shifted quickly to an identically sized storage array. The readout process from the storage array is the same as in a full-frame device, but the frame rates are increased because the image array can begin the next exposure while the readout process is taking place.

Frame-Transfer (FT) Devices. The FT CCD architecture is similar to that of the FF CCD, except that FT CCDs have a separate, identical parallel register, called a storage array, which is not light sensitive (see Figure 2). The idea is to quickly shift a captured scene from the image array to the storage array. Readout off chip from the storage register is then performed as described in the FF device while the storage array is integrating the next frame.

The advantage of this architecture is that a continuous or shutterless/strobeless operation is achieved, resulting in faster frame rates. Performance is compromised, however, because integration is still occurring during the image dump to the storage array, which results in image smear. Because twice the silicon area is required to implement this architecture, FT CCDs have lower resolutions and higher costs than FF CCDs.

Interline (IL) Devices. IL CCDs address the shortcomings of FT devices by separating the photo-detecting and readout functions with isolated

Figure 3. In an interline CCD, each pixel is composed of a photodiode and an associated light-shielded CCD. After exposure, the charges in each photodiode are immediately transferred to the adjacent CCD, where the readout process is conducted. Frame rates increase because the transfer rate is even faster than a frame-transfer device.

photosensitive regions between lines of nonsensitive or light-shielded parallel readout CCDs (see Figure 3). After integrating a scene, the signals collected in the pixels are simultaneously transferred to the light-shielded parallel CCD. Transfer to the output is then carried out in much the same way as in FF and FT CCDs. During readout, the next frame is being integrated, thus achieving a continuous operation and a higher frame rate. Because of the architecture, the image smear that occurs in IL CCDs during readout is significantly reduced.

The major disadvantages of IL CCD architectures arise from the complexity of the devices, which leads to higher unit costs and lower sensitivity. Lower sensitivity occurs because less photosensitive area (i.e., a reduced aperture) is present at each pixel because of the associated light-shielded readout CCD. Furthermore, quantization, or sampling, errors are greater because of the reduced aperture. Lastly, some IL architectures using photodiodes suffer image lag as a consequence of charge transfer from photodiode to CCD.

1. Exposure, which converts light into an electronic charge at discrete sites called pixels
2. Charge transfer, which moves the packets of charge within the silicon substrate
3. Charge-to-voltage conversion and output amplification.

Converting Light to an Electronic Charge. An image is acquired when incident light in the form of photons falls on the array of pixels. The energy associated with each photon is absorbed by the silicon, and a reaction takes place that creates an electron-hole charge pair (i.e., an electron). The number of electrons collected at each pixel is linearly dependent on light level and exposure time and nonlinearly dependent on wavelength.

Many factors can affect the ability to detect a photon. Thin films of materials intentionally grown and deposited on the surface of the silicon during fabrication can absorb or reflect the light, as in the photocapacitor's case. Photons are absorbed at different depths in the silicon, depending on their wavelength. There are instances in which photon-induced electrons cannot be detected because of the location within the silicon where they were created.

Potential Wells and Barriers. CCDs follow the principles of basic metal oxide semiconductor (MOS) device physics. A CCD MOS structure simply

Figure 4. Charge is collected in potential wells created by applying a voltage to the polysilicon, or gate, electrode. The charge is confined in the well associated with each pixel by surrounding zones of higher potential, called barriers.

consists of a vertically stacked conductive material (doped polysilicon) overlying a semiconductor (silicon), separated by an insulating material (silicon dioxide).

By applying a voltage potential to the polysilicon, or gate, electrode, the electrostatic potentials in the silicon can be changed. With an appropriate voltage, a potential well can be formed that can collect the localized electrons created by the incident light. The electrons can be confined under the gate by forming zones of higher potentials, called barriers, surrounding the well. Depending on the voltage, each gate can be biased to form a potential well or a barrier to the integrated charge (see Figure 4).

Charge Transfer Techniques. Once charge has been integrated and is held in the pixel architecture, you must have a means of getting the

Figure 5. CCD shift registers are formed by a chain of gates along one axis forming a column. By changing the polarity of the gates in sequence, the charge packet is forced by electrostatics to move along the chain. In a four-phase CCD, four gates are used to define each pixel.

charge to the sense amplifier, which is physically separated from the pixels. The common methods used today involve four charge-transfer techniques. Keep in mind that as you move the charge associated with one pixel, you are at the same time moving the charge in all the pixels associated with that row or column.

Four-Phase (4) CCDs—CCD shift registers are created by defining polysilicon electrodes so that they make up a long chain of gates along one axis, forming a column. If you apply a high voltage to one of the gates, a potential well is formed beneath the gate, while a low voltage forms a potential barrier.

Four gates are used to define a single pixel. As Figure 5 shows, during integration, if you hold high voltage on the 1 and 2 gates while keeping low voltage on the 3 and 4 gates, you can form a potential well that integrates and collects a photo-induced charge for pixel Pn. If the 1 and 3 gates change their polarity (i.e., the 1 gate goes from high to low voltage, and the 3 gate goes from low to high voltage), the charge packet is forced by electrostatics to move beneath the 2 and 3 gates. The 2 and 4 gates reverse their polarity, and the charge is moved further, occupying the well formed by the 3 and 4 electrode. The process is continued until the charge packet lies beneath the 1 and 2 gates of the next pixel (pn+1), which completes one transfer cycle. The cycle is repeated until all charge packets have reached the output.

Three-Phase (3) CCDs—3 CCDs are similar to 4 CCDs except that the number of barrier-biased gates separating the well-biased electrodes is reduced from 2 to 1 and the timing requirements change slightly. In this technique, charge resides under 1 while 2 and 3 are held in the barrier state. 2 is brought to the high level, followed shortly by 1 assuming the low level. The charge, now residing under the 2 gate, can be shifted under the 3 gate by manipulating 2 and 3 in the same way as described for the 4 CCD.

The transfer cycle is completed when the charge is shifted to the 1 gate of the next pixel. The advantage of this operation is that only three gates are required to define a pixel, allowing for CCDs with higher density and higher resolution. The disadvantage of 3 CCDs compared with 4 CCDs is that more elaborate clocking must be generated to drive the device.

Pseudo Two-Phase (P2) CCDs—P2 CCDs mimic a 4 operation but require only two-phase clocks to implement the transfer procedure. Each phase is tied to two gates instead of one. To ensure that pixels are not mixed during the transfer operation, alternate gates are processed so that the electrostatic potentials occur at different levels for a given gate bias. Once this is achieved, proper transfer can occur using only two phases, thus reducing the complexity required for driving the CCD. However, extra processing is required, which adds to the cost of the device.

True Two-Phase (T2) CCDs—The T2 transfer technique reduces the

Figure 6. In a true two-phase CCD, only two gates are used to define each pixel. A true two-phase CCD has the potential for very high densities and resolutions at the expense of much higher processing to handle the complex clocking required.

number of gates per pixel and the number of CCD drive phases to only two (see Figure 6). You achieve T2 transfer by creating a stepped potential beneath each gate, as contrasted with the P2, in which two adjacent gates are required to form the stepped potential. A T2 CCD is clocked like the P2 CCD, but T2 technologies have the capacity for high densities and high resolutions. Unfortunately, with this type of CCD, the processing becomes more extensive, adding to its cost.

Virtual-Phase (V) CCDs—V CCDs reduce the number of gates per pixel and the number of CCD drive phases to only one. V CCDs have no polysilicon electrodes between the 1 gates. This makes the V CCD more sensitive to light (especially in the blue range) because of the reduced overlying topography, which can absorb or reflect the light. This technique preserves charge transfer efficiency by creating a stepped and pinned potential in the silicon. The architecture can also achieve high pixel densities. However, V CCDs have high clock swings, which are required by 1, and performance degradations presumably caused by the multiple implant complexities.

Readout Techniques. The packets of charge are eventually shifted to the output sense node, where the electrons (which represent a charge) are converted to a voltage. Conventional techniques usually use a floating-diffusion sense node followed by a charge-to-voltage amplifier, such as a source follower. It is called a floating diffusion because its potential level varies depending on the amount of charge present on the node.

Source followers are used to preserve the linear relationship between light in, electrons generated, and voltage output. The process begins by resetting the floating diffusion through a reset gate and reset drain, which dictates the reset potential. The reset or zero signal is converted to a voltage and immediately sent off chip, where it is processed as a reference level. The charge is then shifted from the last phase in the CCD and dumped onto the floating diffusion. The resulting change in potential is converted to a voltage and sensed off chip. The difference between the reference or reset level and the potential shift of the floating diffusion level determines the signal.

Color Sequential Systems—A color image can be created using a CCD by taking three successive exposures while switching in optical filters having the desired RGB characteristics. The resulting image is then reconstructed off chip. The advantage of this technique is that resolution can remain that of the CCD itself. The disadvantage is that three exposures are required, reducing frame times by more than a factor of three. The filter-switching assembly also adds to the mechanical complexity of the system.

Three-Chip Color Systems—Instead of switching colors with a color filter wheel, three-chip color systems use optics to split the scene onto three separate image planes. A CCD sensor and a corresponding color filter is placed in each of the imaging planes. Color images can then be detected at once by synchronizing the outputs of the three CCDs, reducing the frame rate back to that of a single-sensor system. The disadvantage of such a system is that complexity is high, effective data rate (bandwidth) is tripled, and registration/calibration between sensors is difficult.

Integral Color Filter Arrays (CFA)—Instead of performing color filtering off chip, you can place filters on chip. This can be performed during device fabrication using dyed (cyan, magenta, yellow) photoresists in various patterns. This approach considerably reduces system complexity. The main problem with this approach is that, unlike film, each pixel can be patterned only as one (primary color system RGB) or two (secondary color systems CMY) colors or a combination of the two. Any choice results in the loss of information, which reduces effective resolution and increases sampling (quantizing) artifacts. Another disadvantage is that off-chip processing is required to fill in the missing color information between pixels, increasing system complexity.

Antiblooming. A problem occurs when CCDs are overexposed. As mentioned earlier, electrons are created at a rate linearly proportional to the amount of exposure of the device to light. If the potential wells in the CCD do not have the capacity to hold the integrated charge, they will "bloom," or spill into adjacent pixels, corrupting scene information.

The blooming can be alleviated by building antiblooming, or overflow, drain structures in the device. Two common antiblooming structures are vertical overflow drains (VOD) and lateral overflow drains (LOD).

VOD devices have built-in electrostatic potential barriers to the biased substrate. The barrier is designed to a level lower than the barriers between pixels. When collected charge exceeds this level, it spills vertically through the silicon and is swept away by the bias on the substrate. This structure increases device complexity; adds to the cost of the device; and usually reduces well capacity, which leads to a lower dynamic range.

Figure 7. At high exposures, the charge can exceed the capacity of the CCD potential wells and spill over, or bloom, into adjacent pixels, corrupting the scene information. A lateral overflow drain adjacent to the integrating pixels collects excess charge spills. The charge is then swept off the chip, providing an antiblooming effect.

One of the problems with VOD structures is that they can handle only limited overexposure. For the most demanding situations, a LOD structure is used. A LOD is implemented on the surface of the silicon, where the rest of the structures reside. In this case, a barrier is created adjacent to the integrating pixels, and charge spills into the drain laterally and is swept off chip (see Figure 7). The disadvantage of such a structure is reduced fill factor or aperture, which leads to reduced photoresponsivity.

A side benefit of incorporating one of these overflow drains is the ability to use that feature to implement electronic exposure or shutter control. Electronic exposure, which is much more accurate and reliable than mechanical shuttering, allows versatile operation for systems or cameras.

Silicon Thinning. As shown earlier, overlying films on the pixels absorb or reflect the light, depending on wavelength. Electrons created at the top surface of the silicon (nominally ultraviolet and blue wavelengths) are also lost because of recombination at the oxide-silicon interface.

To increase the response of the sensor, the backside of the wafer is thinned to depths of ~10-15 microns. With the proper thinning, the CCD is illuminated from the backside, and UV and blue response is increased significantly. Thinning is restricted to FF and FT architectures without VOD structures. Unfortunately, thinning the device to such depths reduces yields and increases costs, and handling becomes difficult as well.

UV Enhancement Coatings. To get around the difficulty of wafer thinning, UV-sensitive phosphors are deposited on top of the CCD. The phosphors, which are transparent above 0.45 mm, absorb the UV and deep blue wavelengths and fluoresce at a longer wavelength. The only disadvantage of using these coatings is the loss in spatial resolution caused by light scattering.

Microlenticular Arrays. IL and LOD architectures suffer from reduced aperture or optical fill-factor, resulting in lower sensitivity. To improve sensitivity, microlenticular arrays are formed over each pixel. The arrays are little lenses (or lenslets) that focus the light that would normally strike the nonphotosensitive areas into regions that are sensitive. Improvements as great as a factor of three can be realized using this technique. Disadvantages include increased processing, lack of uniformity of the lenses across the array, and increased packaging difficulties.

High-Speed CCDs. The limiting factor in developing high-speed CCDs is designing an on-chip amplifier that maximizes speed but does not consume a lot of power. Increased power dissipation tends to cause localized heating in the chip, which degrades uniformity. To overcome this problem, multiple outputs are used to partition the device into blocks so that data can be read in parallel. If two outputs are used, the effective data rate increases by a factor of two. The more parallelism used, the less bandwidth required for each output.

Problems arise in processing so many outputs. Because of the capacitance associated with the MOS-based CCD device, high-speed shift registers are sometimes limited by the off-chip clock driver. Another problem associated with high-speed CCDs is the inherent noise coupling that occurs from system to device because of the capacitive nature of the CCD.

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