Ph.D. Proposal Presentation by Siva P. Gurrum
Friday, August 6, 2004

(Dr. Yogendra K. Joshi, Chair)

"Thermal Modeling and Characterization of Nanoscale Metallic Interconnects"

Abstract

On-chip metallic interconnect structure in microprocessors is projected to continually change with each technology node. Smaller feature sizes, higher current densities, low-k dielectrics and higher number of metal levels are expected to increase temperature rise due to Joule heating. Higher temperatures reduce performance and reliability of microprocessors. It has become necessary to incorporate thermal design into the overall design, from the beginning. Due to the small sizes of next generation interconnects, classical Fourier law based heat conduction analysis is insufficient to predict temperature rise accurately. In addition, due to large number of features, an efficient and reliable thermal design approach is necessary.
In this research, an integrated thermal modeling methodology is proposed to predict the thermal field in an interconnect multi-stack, including microscopic size effects due to dimensions comparable to mean free path of electrons. A compact thermal modeling methodology is proposed for thermal field prediction based on effective properties and size effect models. A numerical approach to simulate detailed electron transport through the solution of Boltzmann Transport Equation (BTE) within the relaxation time approximation and linear response is developed. High spatial resolution thermal imaging of nanoscale interconnects based on Scanning Joule Expansion Microscopy (SJEM) is proposed to critically examine microscopic size effect models.


Primary outcome of this study is expected to be an efficient and accurate thermal modeling methodology for next generation nanoscale metallic interconnects.