MS Thesis Presentation by George C. Lo
Monday, August 2, 2004
(Dr. Suresh Sitaraman, Chair)
"Electroplated Compliant High-Density Interconnects For Next-Generation Microelectronic Packaging"
Dramatic advances are taking place in the microelectronic industry. The feature size continues to scale down and it is expected that the minimum feature size on the integrated circuit is expected to reach 9 nm by 2016, and there will be more than 8 billion transistors on a 310 cm2 chip, according to various available roadmaps. Subsequently, this reduction in feature size would require the first-level input-output interconnects to decrease in pitch size to meet the increased number of transistors on the chip. Also, to minimize the on-chip interconnect delay, development of low-K dielectric/copper will become increasingly common in future devices. However, due to the low fracture strength of low-K dielectric, it is essential that the first-level interconnects exert minimal force on the die pads and therefore, do not crack or delaminate the low-K dielectric material. It is also preferable to have a wafer-level packaging approach to facilitate test-and-burn in and to produce known-good dies. Based on these growing demands from the microelectronics industry, there is a compelling need to develop innovative interconnect technologies.
This thesis aims to develop one such innovative interconnect – G-Helix interconnect. G-Helix is a scalable lithography-based wafer-level electroplated compliant interconnect that has the potential to meet the fine-pitch first-level chip-to-substrate interconnect requirements. The three-mask fabrication of G-Helix is based on lithography, electroplating and molding (LIGA-like) technologies, and this fabrication can be easily integrated into large-area wafer-level fine-pitch batch processing. In this work, the fabrication, assembly, experimental reliability testing, and numerical physics-based modeling of the G-Helix interconnects will be presented.
The fabrication of the interconnects will be demonstrated at 100µm pitch
on a 20 x 20 mm die in a class 10/1000 cleanroom facility. The wafers with compliant
interconnects will be singulated into individual dies and assembled on substrates
using Pb/Sn eutectic solder. The assembly will then be subjected to air-to-air
thermal cycling and the reliability of the compliant interconnect will be assessed.
In addition to the thermo-mechanical reliability testing, some of the dies with
free-standing interconnects will also be used for measuring the compliance of
the interconnects by compressing with a nanoindenter. In parallel to the experimental
research, a numerical analysis study will also be carried out. The numerical
model will use direction-, temperature, time-dependent, and time independent
material constitutive properties as appropriate. The thermo-mechanical fatigue
life of the compliant interconnect assembly will be determined and compared
with the experimental data. Recommendations will be developed for further enhancement
of reliability and reduction in pitch size.