(Dr. Suresh Sitaraman, advisor)
"Helix-Type Compliant Off-Chip Interconnects for Microelectronic Packaging "
The rapid advances in IC design and fabrication continue to challenge and push the microelectronic packaging industry in size, performance, cost, and reliability. The minimum feature size in IC components will reach the scale of about 25 nm by 2010 according to International Technology Roadmap for Semiconductors (ITRS) 2001, requiring the area-array off-chip interconnect pitch to be under hundred microns. Under this fine pitch, not many off-chip interconnects can meet the requirements of reliability, performance, cost, and manufacturability. This bottleneck will limit the future progress of microelectronic industry. We are developing a new technology which is called helix-type compliant off-chip interconnect to address some of the limitations with current off-chip interconnects. This proposed research will cover the full range of design, optimization, fabrication, assembly and reliability assessment of this novel interconnect technology through analytical, numerical and experimental investigations.
Two kinds of helix-type compliant interconnects, ?-helix and G-helix, have been designed for different applications. The fabrication of the helix-type compliant interconnects is based on the lithography, electroplating and molding (LIGA-like) technologies, and this fabrication can be integrated into wafer-level batch processing. The helix-type off-chip interconnects are expected to have good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. The geometry effects on the mechanical compliance and electrical parasitics have been studied. However, it is found that the helix-type interconnect with excellent mechanical compliance may not have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), optimization has been done. Moreover, physics-based predictive reliability models have been built to evaluate the effect of package weight on the free-standing compliant interconnect and the thermo-mechanical reliability. The heat removal capability of the helix-type compliant interconnect will also be studied. Finally a comprehensive design guideline for compliant off-chip interconnects will be established based on the comprehensive thermal-mechanical-electrical studies.