Ph.D. Proposal Presentation by Jian Zhang
Monday, August 18, 2003

(Dr. Daniel Baldwin, advisor)

"In-Process Stress Analysis of Flip Chip Assembly and Reliability Assessment during Environmental and Power Cycling Tests"

Abstract

The need for microelectronic product miniaturization and increased functionality is driving the demand for flip chip microsystems packaging. The C4 (Controlled-Collapse-Chip-Carrier) interconnection technology has been extended to direct chip attach (DCA) onto organic substrates as opposed to conventional ceramic substrates. This provides a promising low-cost packaging technology for MEMS, bio-medical sensors, and optoelectronics devices. There are some challenges in the flip chip on organic board packaging technology. Under processing or operating conditions, the CTE mismatch-induced stresses, substrate warpage-induced stresses, and underfill encapsulation stresses pose a severe reliability concern of flip chip microsystems. It is necessary to characterize the packaging process-induced stresses in the flip chip on organic microsystems as well as the warpage of the organic substrate.

In this research, comprehensive research in flip chip packaging process development, process characterization, and reliability assessment are conducted using experimental and analytical approaches. The flip chip packaging process for fine-pitch (254µm) high-I/O count (1764 bumps) microsystems is developed using a capillary flow underfill encapsulant. Flip chip test vehicles are assembled using 11.58 ×11.58 mm ATC4.1 piezoresistive sensor chips and 50µm line/space organic high-density-interconnect substrates. The in-plane stresses of the flip chip microsystems are experimentally characterized by the full area array piezoresistive stress sensors at each packaging process phase. In addition, the in-situ substrate warpage is measured by a shadow moiré system. A power cycling accelerated life test system is developed to investigate the interconnection field reliability of the flip chip microsystems. The failure modes are validated by scanning acoustic microscopy (SAM), X-ray, cross-section analysis, and scanning electron microscopy (SEM). A physics-based analytical model is also developed to predict the process-induced stresses in the flip chip microsystem, the substrate warpage, and the field reliability of the interconnections. Virtual design optimization and design for field reliability are achieved by utilizing this validated model.