(Dr. Suresh K. Sitaraman, advisor)

"Thermo-Mechanical Evaluation of Interfacial Integrity in Multilayered Microelectronic Packages"

Abstract

To meet the dramatic changes in the computer, telecommunications, automotives, and consumer electronics industries, a new microelectronics packaging paradigm called “System-On-Package (SOP)” is being pursued. This highly-integrated package will dramatically reduce the package size and fabrication cost and increase reliability and performance, which can be accomplished by integrating all system-level components including ultra high-density wiring (HDW), resistors, capacitor, inductors and optoelectronics into a multilayered substrate. Like other multilayered structures, significant interfacial stresses could build up at interface between dissimilar materials. Such thermally-induced stresses could cause interfacial delamination that could lead to functional failure of microelectronic packages.

The objective of the research is to understand the interfacial integrity of multilayered microelectronic packaging structures under monotonic and cyclic loading. A framework for evaluation of interfacial integrity of multilayered electronic packaging structures ahs been established through this research. Some important thermo-mechanical reliability aspects related to interfacial phenomenon such as free-edge interfacial stresses, delamination initiation at free edges, interface characterization, and interfacial delamination propagation under monotonic and cyclic loading have been attacked. Analytical and numerical models have been developed to determine interfacial stresses in asymmetric, anisotropic multilayered structures. The concept of the free-edge Stress Intensity Factor (SIF) has been applied to predict the initiation of interfacial delamination. The critical free-edge SIF has characterized by simple shear tests as opposed to specially designed, complicated tests. Interfacial fracture resistance has measured with specially-designed sandwich specimens. Fatigue tests were conducted to study interfacial delamination propagation under cyclic loading. The methodologies and models developed in this research have been used to analyze SOP test vehicles and results have been compared with thermal reliability test. The methodology developed in the research can be extended to other types of microelectronic packaging structures as well.