M.S. Thesis Presentation by Laam Angela Tse
Tuesday, November 20, 2001

(Dr. Peter Hesketh, advisor)

"MEMS Packaging with Stereolithography"


Fabrication of high aspect ratio microstructures is one of the biggest challenges in microfabrication technology.  A key limitation is that the complexity of the microstructure is limited to a projection of a 2-D masking layer.  Stereolithography is conventionally used for rapid prototyping of new products and the minimum feature size and dimensional tolerances are not as critical.  However in MEMS applications, several aspects, such as the minimum feature size, dimensional tolerance, insertion of electrical wires and tubes into the build and being able to form parts on top of the silicon wafer, become important for packaging.  In this work, we have investigated the capability of stereolithography technology to overcome these limitations in the microfabrication of high aspect ratio structures.  Stereolithography can fabricate complicated 3D microstructures within a few hours during a single step process.  The micromachining cost of high aspect ratio microstructure is higher than other IC processes and the processing time is long.  The stereolithography costs are much lower than traditional micromachining for small volume manufacturing.

In this project, a commercial stereolithography machine is used for fabrication and the machine has feature size limitation of ~400mm and step size limitation of ~50mm.  The capabilities of stereolithography technology and the characteristics of the final parts are being investigated for applications in the MEMS area.  The fabrication process and the functionality of the final parts studied, include 1) miniature chemical sensor packages, 2) gas chromatography column for chemical gas detection, 3) directly build packages around the interdigitated electrodes on silicon for miniature chemical analysis system on a chip and 4) mechanical components, such as sliders and helical spring, for system integration.  In order to lower the cost and shorten the time of MEMS packaging, wafer level packaging methods have also been studied.