M.S. Thesis Presentation by Ryan Thorpe
Friday, August 27, 1999

(Dr. Daniel Baldwin, advisor)

"Reliability Analysis of Flip Chip on Board Assemblies Using No-Flow Underfill Materials"

Abstract

Advanced electronics packages are increasing in production volumes dramatically.  One of the fastest growing segments in the advanced packaging sector is flip chip on board (FCOB).  FCOB processing involves the interconnection of unpackaged integrated circuits (ICs) directly to low cost organic substrates.  In many cases, current assembly techniques for FCOB are not capable of achieving the high throughputs required for integrated Surface Mount Technology (SMT) processing. A new FCOB assembly technique that is compatible with SMT processing has recently been proposed.  The new process combines solder reflow and underfill cure into a single thermal process to reduce manufacturing time and cost by over 50 percent. Underfilling the chip using a compression flow process rather than a capillary flow process eliminates lengthy underfill flow times.

Although previous work has demonstrated the feasibility of the high-throughput process, the reliability of these FCOB assemblies is not well characterized.  The “no-flow” underfill materials used in the process are substantially different from conventional underfill materials.  Long term reliability of the new underfill materials must be demonstrated before the process will gain acceptance in the electronics assembly industry.  The primary goal of this project is to assemble a series of test vehicles to evaluate the reliability of “no-flow” underfill materials and analyze the modes of failure.  The reliability performance of four underfill materials is evaluated using six test vehicles.  Accelerated reliability tests performed on the test vehicles included liquid/liquid and air/air thermal cycling, Autoclave, and J-STD-020A Level 1&3 preconditioning.  No-flow underfill materials tested in this work have demonstrated the ability to survive in excess of 1000 cycles of liquid/liquid thermal shock, survive more than 100 hours of autoclave, and pass J-STD-020 Level 3 preconditioning.  Analysis of failed assemblies identified six primary modes of chip failure: delamination at the chip/underfill interface, solder fatigue cracks, underfill cracks, substrate cracks, corrosion, and board degradation.