M.S. Thesis Presentation by Rajiv Raghunathan

(Dr. Suresh Sitaraman, advisor)

"Virtual Qualification Methodology for Next-Generation Area-Array Devices:

Abstract

Flip Chip on Board (FCOB), Chip-Scale Packages (CSPs), Flip Chip on Flex (FCOF) and Flip Chip on Polymer Stud Grid Array (FC-PSGA) are emerging technologies that are being increasingly used in the electronic packaging industry.  As these packaging technologies are relatively new, guidelines for qualifying these devices are not clearly established.   In the absence of specific guidelines, the industrial practice is to subject the devices to military-standard qualification cycles with limited consideration for the application of the product.  Also, with the ever increasing complexity of such packages and with the continued reduction in time to market, building and assembling prototype systems and subjecting the systems to extensive qualification tests to achieve high reliability is time consuming and expensive; also such a build and test approach does not provide adequate insight into the failures.

The number of thermal cycles, the temperature range, and the time of dwell used for qualifying a microelectronic package should be based on the type of application the package is intended for.  Therefore, the primary goal of the research is to develop qualification guidelines for FCOB and FCCSP packages used in implantable medical devices, automotive applications, computer applications and portables, taking into consideration the thermal history associated with the field conditions.  The accumulated equivalent inelastic strain per cycle and the maximum strain energy density over one cycle have been used as a damage parameter to correlate solder fatigue damage during field use and thermal cycling. Different temperature regimes are explored to reduce the time required for qualification. The process mechanics of substrate fabrication and component assembly, time- and temperature-dependent material behavior and critical geometric features of the assembly are taken into consideration while developing the comprehensive virtual qualification methodology.  Results from the modeling methodology have been validated against experimental data for Polymer Stud Grid Array devices.  Suitable design guidelines to minimize the thermal stresses in the die have also been developed for the FCOF.