(Dr. Suresh Sitaraman, advisor)
"Damage-Metric Based Thermal Cycling Guidelines for Area Array Packages used in Harsh Thermal Conditions"
The temperature range, the time of dwell, the ramp times, and the number of cycles are the parameters most commonly used to define qualification parameters for micro-electronic packages. As reliability testing at field conditions will take several years to complete, acceleration has to be incorporated in the test cycling. A fundamental requirement for test acceleration is that the failure mechanisms should only be accelerated and not altered during the test. Currently large variations in test conditions exist between one company or standard and the next, even for the same type of product and expected use. One cause of the variation is a lack of a physics-based correlation between failure mechanisms, field conditions, and qualification parameters. This work is intended to develop a virtual reliability methodology that can take into consideration failure mechanisms, field conditions, and qualification parameters to reduce the amount of expensive testing that is required to qualify electronic packages.
There are varieties of field conditions under which electronic packages
operate. This work will focus on packages intended to be used in
semi-harsh automobile and harsh military applications. For the packages
used in military applications, the effect of the underfill on solder joint
reliability is investigated, as is the effect of board stiffness. The accumulated
equivalent inelastic strain and the strain energy density will be used
as damage parameters to correlate solder fatigue damage during field use
and qualification testing. Additional failure mechanisms such as
underfill delamination and die cracking will be investigated. The
board level assembly process mechanics, visco-plastic material properties
and critical geometric features of the packages are taken into consideration
while developing the methodology, and the approach is validated against
experimental test data.