M.S. Thesis Presentation by Seong Joon Ok
Tuesday, December 17, 2002

(Dr. Daniel Baldwin, advisor)

"High Density, Aspect Ratio Through-Wafer Electrical Interconnect Vias for MEMS Packaging"

Abstract

The commercialization of Micro-Electro-Mechanical-Systems (MEMS) devices is hindered mainly due to high cost and inadequate packaging solution. In modern microsystem packaging, high I/O is one of the key functional requirements, and the vertical electrical interconnection is intended for improved space efficiency. The focus in this thesis is on fabrication of high density, aspect ratio Through-Wafer Electrical Interconnect (TWEI). Highly improved high aspect ratio TWEI vias for MEMS packaging were designed and fabricated. This updated TWEI knowledge can be used for a modular, direct-chip attach, wafer-level MEMS packaging.

TWEI can be fabricated before MEMS device fabrication (Pre-Processed TWEI). Also, TWEI can be fabricated after MEMS device fabrication (Post-Processed TWEI). Both Pre-Processed TWEI and Post-Processed TWEI were fabricated, and their electrical performances were obtained. The high aspect ratio through-wafer vias were dry-etched by using Inductively Coupled Plasma (ICP) etching tool followed by depositing silicon dioxide insulation layer. Various techniques such as sputtering copper, electroplating copper, and depositing Low Pressure Chemical Vapor Deposition (LPCVD) phosphorus doped polysilicon were used as through-wafer via conductive layers.