Ph.D. Thesis Defense by Lunyu Ma
Tuesday, June 17, 2003
(Drs. Suresh Sitaraman and Robert Fulton, co-advisors)
"Design and Development of Stress-Engineering Compliant Interconnect in Microelectronic Packaging"
With the increased demand for lower cost, smaller profile and better performance in microelectronic devices, the feature size of integrated circuits (ICs) is continuously reduced into sub-micron scale. An effective solution to electronic packaging, especially the chip-to-substrate interconnection technology, must be provided to fit the rapid development of semiconductor industry well. An innovative technology, called stress-engineered compliant interconnect, is being developed to meet the requirements of International Technology Roadmap for Semiconductor (ITRS) requirements for year 2016 and even beyond. The thin film metal is stress-engineered during sputtering deposition on the wafer, patterned by photolithography, and later curls up automatically due to the intrinsic stress gradient through the thickness. The unique fabrication of this interconnect is cost competitive and can be easily integrated into wafer-level packaging (WLP).
The stress-engineered compliant interconnect is expected to have a different thermo-mechanical performance, compared with the traditional rigid C4 interconnect. A new assembly approach has been developed with respect to the fine pitch and high compliance of this stress-engineered compliant interconnect. To understand the thermo-mechanical reliability of this compliant interconnect, test vehicles have been fabricated, assembled and subjected to thermal cycling test. The thermo-mechanical reliability of the contact interconnects is assessed through the measurement of electrical resistance during thermal cycling. In parallel to the experiments, finite-element models have been developed to predict the thermo-mechanical reliability of the compliant interconnect assembly. The sliding contact reliability is also considered for the free-air non-soldered assembly under the constant normal compressive load and the cyclic tangential frictional load caused by the cyclical temperature excursion. In addition, an alternative compliant interconnect, called ‘J-Spring’, is also proposed to improve the in-plane compliance. General design guidelines of the stress-engineered compliant interconnect reliability are proposed