(Dr. Suresh Sitaraman , advisor)
"Study of the Thermo-Mechanical Reliability of Area-Array Packages"
Flip Chip on Board (FCOB) and Chip-Scale Packages (CSPs) have just begun to find their niche in the electronic packaging industry. Compared to traditional surface mount technology (SMT), FCOB and CSP have smaller circuit board footprints, offer higher performance, increased functionality, and are expected to become cost-competitive. However, reliability is of great concern in FCOB and CSPs due to the presence of several tightly-spaced dissimilar materials and due to the larger influence of the silicon die on the stress-strain distribution in the assembly.
The objective of this research is to develop models to understand the reliability of FCOB and to extend such models for a CSP that employs flip-chip on a rigid organic interposer. The models determine the stresses due to underfill cure, and during subsequent thermal cycling. The viscoelastic behavior of the underfill and the creep behavior of the solder joints are taken into consideration, and the assembly is assumed to be stress free at underfill cure temperature. The curing-induced die stresses and their evolution with thermal cycling have been validated against experimental data. A study has also been performed on the effect of different underfill materials and their cure profiles on die stresses.
The FCOB models have been extended to incorporate the manufacturing
processes in a flipchip-based CSP with a focus on second-level interconnects.
Power-law creep model has been used for the solder and has been compared
against Anandís viscoplastic model. Design rules against failures
such as die cracking and solder cracking have been developed.