M.S. Thesis Presentation by Francis C. Classe
Friday, June 27, 2003

(Dr. Suresh Sitaraman, advisor)

"Asymmetric Thermal Cycles: A Different Approach to Accelerated Reliability Assessment of Microelectronic Packages"


Rapid advances in the electronic industry combined with the short turn-around in product development have made it necessary to explore several alternative approaches for accelerated qualification of microelectronic packages without compromising their reliability. One of these techniques that is currently practiced by industry is to subject these packages to accelerated thermal cycles, based loosely on military and other standards. The thermal profiles for these accelerated thermal cycles are symmetric by nature. In other words, the dwell time at the high temperature is the same as the dwell time at the low temperature.

The primary objective of this thesis is to examine if the widely practiced symmetric accelerated thermal cycles can be replaced with asymmetric thermal cycles, and by doing so, whether the time taken for accelerated thermal cycling can be reduced. To prove such a hypothesis that asymmetric cycles can replace symmetric cycles without compromising reliability; an experimental and theoretical program has been developed.

As part of the experimental program Tessera™ MicroBGA components were assembled on organic substrate and subjected to both symmetric and asymmetric accelerated thermal cycling, with a temperature range of –65°C to 150°C and of –40°C to 125°C. The MicroBGA packages are daisy chained test vehicles, and in situ resistance measurements were taken to assess solder joint reliability. In parallel, 2D, 3D, and Generalize Plane Deformation numerical models have been developed to model the viscoplastic behavior of the solder joints and to predict the solder fatigue life under both symmetric and asymmetric accelerated thermal cycling. Inelastic strain and strain energy density were used as damage metrics to predict solder joint fatigue life. The predicted results from the numerical models have been compared with the experimental data, the predicted results agree with the experimental data. It is shown through this work that the asymmetric accelerated thermal cycles require less time for microelectronic package qualification than comparable symmetric cycles, and do not compromise the package reliability.