Raghuram V. Pucha

Senior Research Engineer

Office:	MARC Building, Room 451
Phone:	404.894.7409
Fax:	404.894.9342
E-mail:

Education

• Ph.D., Indian Institute of Science, Bangalore, 1995
• M.E., Madras Institute of Technology, India, 1990
• B. Tech., Nagarjuna University, India, 1988

Research Areas

• Computer-Aided Engineering & Design and Mechanics of Materials; Failure mechanism-based analysis and system-design-for-reliability of advanced material structures, fatigue and microscale plasticity of microelectronics materials, and computational mechanics.

Representative Publications

• R. V. Pucha, et al. 2004. Materials and Mechanics Challenges in SOP-Based Convergent Microsystems. Micromaterials and Nanomaterials, A publication series of the Micro Materials Center Berlin at the Fraunhofer Institute IZM, 3, 16-29.
• R. V. Pucha, G. Ramakrishna, S. Mahalingam and S. K. Sitaraman. 2004. Modeling Spatial Strain Gradient Effects in Thermo-Mechanical Fatigue of Copper Micro-structures. International Journal of Fatigue 26(9), 947-957.
• R. V. Pucha, K. Tunga, J. Pyland, and S. K. Sitaraman, 2004. Accelerated Thermal Cycling Guidelines for Electronic Packages in Military Avionics Thermal Environment. Transactions of the ASME - Journal of Electronic Packaging 126(2), 256-264.
• R. V. Pucha, et al. System-Level Reliability Assessment of Mixed-signal Convergent Microsystems. IEEE Transactions on Advanced Packaging 27(2), 438-452.
• R. V. Pucha, J. Pyland, and S. K. Sitaraman. 2001. Damage Metric-based Mapping Approaches for Developing Accelerated Thermal Cycling Guidelines for Electronic Packages. International Journal of Damage Mechanics 10(3), 214-234.